1. Field of the Invention
The invention relates to a semiconductor memory device, particularly, a semiconductor memory device which reads out data stored in a memory cell transistor by charging a bit line connected to the memory cell transistor and then discharging the bit line according to the data stored in the memory cell transistor.
2. Description of the Related Art
Recently, the nonvolatile memory is used not only for consumer goods such as a mobile, a digital camera and the like but also for on-vehicle, aerial or medical equipments, an ID card and the like which require high reliability in data storage.
The EEPROM (Electronically Erasable and Programmable Read Only Memory) is known as a general nonvolatile memory. This stores binary or multivalued digital data depending on whether or not a predetermined charge amount is accumulated in a floating gate and reads the digital data by sensing the change of conduction of a channel according to this charge amount. This EEPROM includes a stacked gate type EEPROM having a structure where a floating gate and a control gate are sequentially stacked on a semiconductor substrate and a split gate type EEPROM having a structure where a floating gate and a control gate face a channel of a semiconductor substrate.
FIG. 3 is a cross-sectional view showing one memory cell transistor MT of the split gate type EEPROM. An n+-type drain 102 and an n+-type source 103 are formed on a front surface of a P-type semiconductor substrate 101 at a given distance from each other, and a channel 104 is formed therebetween. A floating gate 106 is formed on a portion of this channel 104 and a portion of this source 103 with a gate insulation film 105 being interposed therebetween. An insulation film 107 thicker than the gate insulation film 105 is formed on the floating gate 106.
A tunnel insulation film 108 is formed covering the side surface of the floating gate 106 and a portion of the upper surface of the thick insulation film 107. A control gate 109 is formed on the tunnel insulation film 108 and a portion of the channel 104.
The operation of the memory cell transistor MT having this structure is as follows. First, when data “0” is written, a predetermined voltage is applied to the control gate 109 and the source 103 (e.g. 0V to the P-type semiconductor substrate 101 and 2V to the control gate 109) and a high voltage (e.g. 10V) is applied to the source 103 to flow a current through the channel 104, and thereby channel hot electrons are injected into the floating gate 106 through the gate insulation film 105. The channel hot electrons injected into the floating gate 106 are held in the floating gate 106 as electric charge.
On the other hand, when the data “0” stored in the memory cell transistor MT is erased, the drain 102 and the source 103 are grounded and a predetermined high voltage (e.g. 13V) is applied to the control gate 109 to flow a Fowler-Nordheim tunneling current through the tunnel insulation film 108, and thereby electrons accumulated in the floating gate 106 are extracted to the control gate 109. By this erasing, the digital data stored in the memory cell transistor MT turns to “1”.
When the data stored in the memory cell transistor MT is read out, a predetermined voltage is applied to the control gate 109 and the drain 102 (e.g. 3V to the control gate 109 and 1V to the drain 102). Then, a cell current Ic flows between the source and the drain according to the charge amount of electrons accumulated in the floating gate 106. When the data “0” is already written, the threshold of the memory cell transistor MT is high and thus the cell current Ic is usually about 0 μA. When the data “1” is already written, the threshold of the memory cell transistor MT is low and thus the cell current Ic is usually about 40 μA. The described technique is described in Japanese Patent Application Publication No. 2000-173278.
As a method of reading data, there are a current sensing method where data stored in a memory cell transistor is judged to be “0” or “1” by comparing a cell current Ic with a reference current Iref, and a voltage sensing method where data stored in a memory cell transistor is judged to be “0” or “1” by converting a cell current Ic into a voltage and comparing the voltage with a reference voltage Vref.
Hereafter, the structure of a read circuit with the voltage sensing method will be described referring to FIG. 4. A plurality of memory cell transistors shown in FIG. 3 is disposed into a matrix, forming a memory array 1. FIG. 4 shows only one memory cell transistor MT. The memory cell transistor MT is provided at an intersection of a bit line BL extending in the Y direction and a word line WL extending in the X direction, where a source 103 is connected to a source line SL extending in the X direction, a drain 102 is connected to the bit line BL, and a control gate 109 is connected to the word line WL.
A numeral 2 designates a sense amplifier comparing the voltage of the bit line BL and a reference voltage Vref (0<Vref<Vcc), which is activated by a sense enable signal SAENB from a read control circuit 3. A numeral 4 designates a precharge transistor precharging the bit line into H level (a supply voltage Vcc). The precharge transistor 4 is configured of a P-channel type MOS transistor, and a precharge enable signal PC from the read control circuit 3 is inputted to the gate thereof through an inverter 5.
The read control circuit 3 is configured of a circuit shown in FIG. 5 having a first delay circuit 31 delaying a read enable signal RDE, a second delay circuit 32 delaying the output of this first delay circuit 31, and an AND circuit 33 performing logical multiplication of the read enable signal RDE and an inverted signal of the output of the first delay circuit 31. Each of the first and second delay circuits 31 and 32 is configured of a resistor and a capacitor. The precharge enable signal PC is obtained from the output of the AND circuit 33, and the sense enable signal SAENB is obtained from the output of the second delay circuit 32.
The operation of this read circuit will be described referring to FIG. 6. When the word line WL turns to H level, the memory cell transistor MT is turned to a selected state. When the read enable signal RDE turns to H level, the precharge enable signal PC turns to H level and keeps it for a period t1. When the precharge enable signal PC turns to H level, the precharge transistor 4 turns on and the bit line BL is charged into H level.
Then, when a period t2 passes, the sense enable signal SAENB turns to H level and the sense amplifier 2 is activated. During this period t2, the data stored in the memory cell transistor MT is read out. In detail, the cell current Ic flows when the data stored in the memory cell transistor MT is “1”, and the bit line BL is discharged into L level (a ground voltage Vss). In this case, the output of the sense amplifier 2 becomes L level. On the other hand, when the data stored in the memory cell transistor MT is “0”, the cell current Ic hardly flows and thus the voltage of the bit line BL keeps H level. In this case, the output of the sense amplifier 2 becomes H level.
The period t1 is determined by the delay time of the first delay circuit 31, and the period t2 is determined by the delay time of the second delay circuit 32.
As described above, the bit line BL is charged and then discharged in the reading operation, and the periods t1 and t2 for charging and discharging (=the reading time) are set by the first delay circuit 31 and the second delay circuit 32, respectively. Therefore, in this read circuit, the periods t1 and t2 are set so that the reading operation can be performed in the worst operation environment taking account of variation in an operation voltage, an operation temperature, a process parameter and so on. This causes a problem that an unnecessary margin is required in the reading time under a condition which is not in the worst environment and thus a high speed reading operation is not achievable.